The Technology
One of the holy grails for the microelectronic industry is to continue device miniaturization in order to increase the operation speed of the device (clock speed) and to pack more devices to reduce the fabrication cost. Therefore, many efforts are made to scale down the device channel length without compromising the main performance figures of merits, which are the subthreshold slope (SS), high “on”/ “off” ratio and low leakage currents to avoid extensive heating of the devices. While it has been extremely challenging to reduce the channel length below 5-10 nm without compromising these parameters using state-of-the-art silicon FIN FETs and NW FETs based on the latest silicon technology, recent nanoscale based devices using carbon nanotubes or 2D materials such as graphene and MoS2, have demonstrated the potential to realize ~ 1 nm channel length.
Another important constraint of current main computer technology is the physical separation between the memory and computation units (known as Von Neumann architecture), which becomes the bottle neck to higher performance computation machines. This challenge recently triggered a lot of attention to alternative computer architectures that combine the memory and computation in the same operation systems i.e. in-memory computation.
None of the current technologies embed the combination of both being in the nanometer scale and enabling memory operation in a single FET device.
A new device structure that is composed of a van der Waals heterostructure combining two different 2-dimensional (2D) materials i.e. In2Se3 and MoS2 is presented. The device is structured such that the channel is composed of MoS2 semiconducting material and it is partially covering a thin layer of 2D ferroelectric In2Se3.
The main operation principle is based on the presents of a stable non-volatile in-plane (IP) polarization at the In2Se3 edge that can either accumulate or deplete electrons at the vicinity of the edge within the MoS2 semiconductor. The polarization can be actuated by either the back-gate electrode due to the intercoupled IP and OOP polarization in In2Se3 or by applying a potential between the In2Se3 and the MoS2 channel. The actuation is done only by the In2Se3 edge and therefore allows to realize an atomic scale channel length. This device also allows to switch between several different channel conductivities due to the stable polarization, thus realizing a non-volatile multi-level operation.
Advantages
- Ultra-small-scale device structure
- High speed operation & low power consumption
Applications and Opportunities
- In-memory computation operation
- Highly sensitive photodetection
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