Information in certain memory cells, such as NAND Flash, is expressed as a charge level in a capacitive cell, which in turn determines a voltage threshold for opening a related transistor gate. Unfortunately, through stray capacitance, the charge in one cell may affect that threshold voltage of a neighboring cell. This is known as inter-cell interference, and is a major contributor to the fact that the threshold voltage of a programmed cell actually falls within a range of values around the nominal one. This, in turn, limits the number of distinct charge levels and thus the information capacity (number of bits) of a cell. The inter-cell interference can be closely estimated based on the technology parameters, the charge levels of a cell and its neighbors, and the programming order. We use this estimate and, set a desired maximum-interference value, and encode the programmed data so that neighboring-cell charge levels that would cause this maximum value to be exceeded are prohibited. By disallowing some combinations we lose storage capacity, but in exchange obtain narrower threshold-voltage ranges around the nominal values.
- Increase the number of distinct levels, thereby increasing information storage capacity, more than offsetting the aforementioned loss (a minor advantage)
- Enable technology shrinking, which increases inter-cell interference, without having to reduce the number of levels by reducing the effect of inter-cell interference, leave more room for other factors and, specifically, permit less accurate and thus faster programming, thus increasing write speed.
Applications and Opportunities
- Can be implemented by the memory chip designer or by the designer of a controller who has access to detailed chip information