The Technology
Machine learning algorithms performed on High Performance Computers (HPC) address complex challenges. These problems are plagued by exponentially growing datasets and pose a major challenge to HPC architects as they cannot be adequately addressed by simply adding more parallel processing. These problems are sequential in the sense that each parallelizable step depends on the outcome of the preceding step, and typically, large amount of data is exchanged (synchronized) between sequential and parallel processing cores in each step. The power consumption spent on such exchange remains and may significantly reduce the power efficiency of the overall system. HPC architectures are thus challenged by the difficulty of synchronizing data among the processing units, having material impact on speedup and power dissipation.
This technology of hybrid computer comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor all implemented in a resistive memory process. This architecture achieves significantly higher performance on large sets at lower power consumption over other parallel on-chip architectures.
Advantages
- A novel resistive GP-SIMD processing-in-memory architecture, enabling hundreds of millions of Processing Units (PUs) on a single silicon die and enhancing effective parallelism and performance, at the cost of reduced power efficiency
- A novel symmetric two-dimensional access method to the resistive memory array, enabling power-efficient and area-efficient access by either the sequential or the SIMD processors
- Enhancing performance and parallelism
Applications and Opportunities
- Any algorithm that utilizes search, dense or sparse matrix multiplication on large data structure. For example, as utilized in machine learning
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