Multithreading processors have been used to improve performance in a single core for the past two decades. One low power and low complexity multithreading technique is Switch on Event multithreading (SOE MT), also known as coarse grain multithreading and block multithreading, where a thread runs inside the pipeline until an event occurs and triggers a thread switch. The state of the replaced thread is maintained by the processor, while the long latency event is handled in the background. While a thread is switched, the in-flight instructions are flushed. The time required to refill the pipeline after a thread switch is referred to as the switch penalty. The switch penalty is usually relatively high, makes SOE MT less popular than simultaneous multithreading. On the one hand, SoE MT is low power but suffers from performance drawback due to the relatively high thread switch penalty. On the other hand Simultaneous Multithreading (SMT) has limitations in the number of threads running in the machinedue to its complexity.
Continuous Flow Multithreading (CFMT) is a new architecture of SoE MT. In CFMT, a novel memory structure – multistate pipeline register (MPR), holds the microarchitectural state of multiple different threads within the execution pipeline stages, where only one thread is active at a given time. The MPRs eliminate the need to flush in-flight instructions and therefore significantly improve performance.
- This architecture can use SRAM or emerging memory technologies to enhance the performance of the processor with no drawbacks
- Improved performance compared to conventional SoE MT processors
- Low power and low complexity as compared to conventional SoE MT processors
- Supporting more threads and consuming significantly less power
Applications and Opportunities
- This architecture can be used in any general purpose processor, suitable for mobile products, personal computers, embedded systems, and servers. These processor will be high performance (high utility of the pipeline) and low power.